The present invention relates to a thin film transistor suitable for use in an active matrix type display apparatus and a method of fabricating the same.
A liquid crystal display (LCD) of an active matrix type which uses thin film transistors (TFTs) has recently been getting attention as a high-quality display apparatus. Dot matrix type LCDs, which have a plurality of pixels arranged in a matrix form, are generally classified into a simple matrix system and an active matrix system.
The active matrix type LCD includes pixels, pixel drive elements (active elements) and signal storage elements (storage capacitors or added capacitors) and drives a liquid crystal in a quasi-static manner which permits each pixel to store data. Each pixel drive element serves as a switch which is switched on or off in response to a scan signal. When the pixel drive element is enabled, a data signal (display signal) is transmitted via that pixel drive element to the associated display electrode, such that the liquid crystal is driven by the data signal. When the pixel drive element is disabled, the data signal is stored in the form of a charge in the associated signal storage element. The liquid crystal is kept driven by the discharging of the charge until the pixel drive element is switched on again. Even though the drive time assigned to a single pixel decreases as the number of scan lines increases, the liquid crystal is sufficiently driven. This prevents the contrast from becoming lower.
Thin film transistors (TFTs) are generally used as pixel drive elements. A TFT has an active layer comprised of a thin semiconductor film formed on an insulator substrate. The semiconductor film preferably includes an amorphous silicon film or a polycrystalline silicon film.
A TFT having an active layer comprised of an amorphous silicon film is called an amorphous silicon TFT, while a TFT having an active layer comprised of a polycrystalline silicon film is called a polycrystalline silicon TFT. The polycrystalline silicon TFT has a greater field effect mobility and higher drive performance than the amorphous silicon TFT. Because of these advantages, the polycrystalline silicon TFT can be used as a logic circuit element as well as a pixel drive element. The use of polycrystalline silicon TFTS, therefore, allows not only the display screen, but also a peripheral drive circuit, located at the periphery of the display screen, to be integrally formed on the same substrate. That is, the display screen and peripheral drive circuit can be formed in the same step.
FIG. 1 is a schematic block diagram of a typical active matrix type LCD. The LCD includes a display panel 101, a gate driver 103, and a drain (data) driver 104.
The display panel 101 has a plurality of scan lines (gate lines) G1, . . ., Gn, Gn+1, . . ., and Gm, a plurality of data lines (drain lines) D1, . . ., Dn, Dn+1, . . ., and Dm running perpendicular to the gate lines G1 to Gm, and a plurality of pixels 102 provided at the intersections of the gate lines G1 to Gm and the drain lines D1 to Dm. The gate driver 103, connected to the gate lines G1 to Gm, applies a gate signal (scan signal) to the gate lines G1 to Gm. The drain driver 104, connected to the drain lines D1 to Dm, applies a data signal (video signal) the drain lines D1 to Dm. Both drivers 103 and 104 form a peripheral drive circuit 105. Either one of the drivers 103 and 104 or both are preferably formed on the same substrate on which the display panel 101 is formed. The LCD is generally called a driver-integrated (driver-incorporated) LCD. The gate driver 103 or the drain driver 104 may be provided on both sides of the display panel 101.
FIG. 2 shows an equivalent circuit of each pixel 102. The pixel 102 includes a liquid crystal (LC) cell LC having a display electrode (pixel electrode) and a common electrode. The LC cell LC is connected to both a TFT 106 and a supplemental capacitor C.sub.S which has a storage electrode and an opposing electrode. The TFT 106 has a gate connected to the gate line Gn, a drain connected to the drain line Dn, and a source connected to the display electrode of the LC cell LC and the storage electrode of the supplemental capacitor C.sub.S. The LC cell LC and the supplemental capacitor C.sub.S form a signal storage element. A voltage V.sub.com is applied to the common electrode of the LC cell LC. A predetermined voltage signal V.sub.R is applied to the opposing electrode of the supplemental capacitor C.sub.S. The common electrode of the LC cell LC is common to all the pixels 102. The LC cell LC has a capacitor formed between the display electrode and the common electrode.
The writing characteristic and holding characteristic of the pixel 102 are important in improving the image quality. The writing characteristic shows how much the LC cell LC and the supplemental capacitor C.sub.S can write desired video signals per unit time based on the specifications of the display panel 101. The holding characteristic shows how long the written video signals can be held. The supplemental capacitor C.sub.S is provided to increase the capacitance of the pixel to improve the holding characteristic. In other words, the supplemental capacitor C.sub.S supplements the LC cell LC with the capacitance.
When a positive voltage is applied to the gate of the TFT 106 via the gate line Gn, the TFT 106 is turned on and a data signal is applied to the drain line Dn. As a result, the capacitor of the LC cell LC and the supplemental capacitor C.sub.S are charged. If a negative voltage is applied to the gate of the TFT 106, the TFT 106 is turned off. At this time, the capacitor of the LC cell LC and the supplemental capacitor C.sub.S hold the applied voltage. In other words, the pixel 102 holds a data signal as the data signal is applied to the associated one of the drain lines D1 to Dm by controlling the voltage on the associated one of the gate line to G1 to Gm. An image is displayed on the display panel 101 in accordance with the held data signal.
FIG. 3 is a cross-sectional view of a part of the conventional LCD display panel 101 which has polycrystalline silicon TFTs 106 of a bottom gate structure. It is preferable that the display panel 101 is of a transparent type.
A polycrystalline silicon film (active layer) 81 of the TFT 106 is formed as follows. First, an amorphous silicon film is formed on a gate insulator film 80 using CVD (Chemical Vapor Deposition). The gate insulator film 80 preferably includes a silicon nitride film 78 and a silicon oxide film 79. Next, an excimer laser beam is irradiated on the surface of the amorphous silicon film to heat the amorphous silicon film, thus forming a polycrystalline silicon film. Laser annealing using an excimer laser beam is called ELA (Excimer Laser Anneal). The ELA scans with a line beam to anneal the entire surface of the amorphous silicon film.
It is preferable that chromium with a high thermal conductivity is used for the gate electrode, 76, of the TFT 106 and the opposing electrode, 77, of the supplemental capacitor C.sub.S. Therefore, the heat energy applied to a part of the amorphous silicon on the gate electrode 76 by the ELA is transmitted via the associated one of the gate lines G1 to Gn, integral with the gate electrode 76, and is diffused outside the irradiation area of the line beam. Consequently, the temperature of the part of the amorphous silicon film on the gate electrode 76 is lower than that of another portion of the amorphous silicon film. In other words, the energy provided to a part of the amorphous silicon film on the gate electrode 76 is lower than the energy given to another part of the amorphous silicon film above the insulator substrate 71. It is preferable to set the laser energy to maximize the grain size of the polycrystalline silicon film 81. When the laser energy exceeds the value that maximizes the grain size, the grain size becomes drastically smaller. Suppose that the laser energy has been set so that the grain size of a channel region 93, defined by a part of the polycrystalline silicon film 81 on the gate electrode 76, becomes maximum. In this case, larger energy than that on the channel region 93 is applied to another part of the polycrystalline silicon film 81. A drain region 82 and a source region 83 are defined in the other part. Accordingly, the grain sizes of the drain region 82 and the source region 83 become smaller. The drain region 82 preferably includes a low-concentration region 82a and a high-concentration region 82b. The source region 83 preferably includes a low-concentration region 83a and a high-concentration region 83b.
FIG. 4 is a graph showing a relationship between the grain sizes of the drain and source regions 82 and 83 and the sheet resistances of both regions 82 and 83 and a relationship between the grain size and the ON current of the TFT 106.
As the grain sizes of the drain and source regions 82 and 83 become smaller, the sheet resistances of the drain and source regions 82 and 83 increase and the ON current of the TFT 106 drops. This is because the sheet resistances of the drain and source regions 82 and 83 serve as a parasitic resistance to reduce the ON current of the TFT 106.
If the ON currents of more than a certain number of TFTs 106 drop to or below a desired value, the display panel 101 becomes defective. Further, if the ON currents of some TFTs 106 drop to or below the desired value, blurring occurs on the display image on the display panel 101. The dropping of the ON currents of the TFTs thus reduces the yield of the display panel 101 and causes a display failure.
Accordingly, it is an object of the present invention to provide a thin film transistor which prevents the ON current from dropping due to a variation in the grain sizes of drain and source regions, and a method which accomplishes the prevention.